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cpldfit:  version O.76xd                            Xilinx Inc.
                                  Fitter Report
Design Name: a_gal                               Date: 12- 7-2011,  5:31PM
Device Used: XC2C32A-4-PC44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
6  /32  ( 19%) 15  /112  ( 13%) 17  /80   ( 21%) 3  /32  (  9%) 22 /33  ( 67%)

** Function Block Resources **

Function Mcells   FB Inps  Pterms   IO       CTC      CTR      CTS      CTE     
Block    Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1       6/16     17/40    15/56     5/16    0/1      0/1      0/1      0/1
FB2       0/16      0/40     0/56     0/16    0/1      0/1      0/1      0/1
         -----    -------  -------   -----    ---      ---      ---      ---
Total     6/32     17/80    15/112    5/32    0/2      0/2      0/2      0/2 

CTC - Control Term Clock
CTR - Control Term Reset
CTS - Control Term Set
CTE - Control Term Output Enable

* - Resource is exhausted

** Global Control Resources **

GCK         GSR         GTS         DGE         
Used/Tot    Used/Tot    Used/Tot    Used/Tot    
1/3         0/1         0/4         0/0

Signal 'CLOCK' mapped onto global clock net GCK0.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
                                    |  I                :     0      1
Input         :   16          16    |  I/O              :    15     24
Output        :    5           5    |  GCK/IO           :     2      3
Bidirectional :    0           0    |  GTS/IO           :     4      4
GCK           :    1           1    |  GSR/IO           :     1      1
GTS           :    0           0    |  
GSR           :    0           0    |  
                 ----        ----
        Total     22          22

End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
   use the default filename of 'a_gal.ise'.
*************************  Summary of Mapped Logic  ************************

** 5 Outputs **

Signal              Total Total Bank Loc     Pin   Pin       Pin     I/O      I/O       Slew Reg     Reg Init
Name                Pts   Inps               No.   Type      Use     STD      Style     Rate Use     State
mapterm             5     16    2    FB1_1   44    I/O       O       LVCMOS18           FAST         
ideio0              1     7     2    FB1_2   43    I/O       O       LVCMOS18           FAST         
ideio1              1     5     2    FB1_3   42    I/O       O       LVCMOS18           FAST         
automap             1     1     2    FB1_4   40    GTS/I/O   O       LVCMOS18           FAST DFF     RESET
mapcond             1     1     2    FB1_5   39    GTS/I/O   O       LVCMOS18           FAST DFF     RESET

** 1 Buried Nodes **

Signal              Total Total Loc     Reg     Reg Init
Name                Pts   Inps          Use     State
sig_mapcond         6     17    FB1_16  TFF     RESET

** 17 Inputs **

Signal              Bank Loc     Pin   Pin       Pin     I/O      I/O
Name                             No.   Type      Use     STD      Style
A<0>                2    FB1_6   38    GTS/I/O   I       LVCMOS18 KPR
A<10>               2    FB1_7   37    GTS/I/O   I       LVCMOS18 KPR
A<11>               2    FB1_8   36    GSR/I/O   I       LVCMOS18 KPR
A<12>               2    FB1_9   35    I/O       I       LVCMOS18 KPR
A<13>               2    FB1_10  34    I/O       I       LVCMOS18 KPR
A<1>                2    FB1_11  33    I/O       I       LVCMOS18 KPR
A<2>                2    FB1_12  29    I/O       I       LVCMOS18 KPR
A<3>                2    FB1_13  28    I/O       I       LVCMOS18 KPR
A<4>                2    FB1_14  27    I/O       I       LVCMOS18 KPR
A<5>                2    FB1_15  26    I/O       I       LVCMOS18 KPR
A<6>                2    FB1_16  25    I/O       I       LVCMOS18 KPR
A<7>                1    FB2_1   1     I/O       I       LVCMOS18 KPR
A<8>                1    FB2_2   2     I/O       I       LVCMOS18 KPR
A<9>                1    FB2_3   3     I/O       I       LVCMOS18 KPR
M1                  1    FB2_4   4     I/O       I       LVCMOS18 KPR
CLOCK               1    FB2_5   5     GCK/I/O   GCK     LVCMOS18 KPR
romacc              1    FB2_6   6     GCK/I/O   I       LVCMOS18 KPR

Legend:
Pin No.   - ~     - User Assigned
I/O Style - OD    - OpenDrain
          - PU    - Pullup
          - KPR   - Keeper
          - S     - SchmittTrigger
          - DG    - DataGate
Reg Use   - LATCH - Transparent latch
          - DFF   - D-flip-flop
          - DEFF  - D-flip-flop with clock enable
          - TFF   - T-flip-flop
          - TDFF  - Dual-edge-triggered T-flip-flop
          - DDFF  - Dual-edge-triggered flip-flop
          - DDEFF - Dual-edge-triggered flip-flop with clock enable
          /S (after any above flop/latch type) indicates initial state is Set
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
              VRF - Vref
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               17/23
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   15/41
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
mapterm                       5     FB1_1   44   I/O     O                 
ideio0                        1     FB1_2   43   I/O     O                 
ideio1                        1     FB1_3   42   I/O     O                 
automap                       1     FB1_4   40   GTS/I/O O                 
mapcond                       1     FB1_5   39   GTS/I/O O                 
(unused)                      0     FB1_6   38   GTS/I/O I     
(unused)                      0     FB1_7   37   GTS/I/O I     
(unused)                      0     FB1_8   36   GSR/I/O I     
(unused)                      0     FB1_9   35   I/O     I     
(unused)                      0     FB1_10  34   I/O     I     
(unused)                      0     FB1_11  33   I/O     I     
(unused)                      0     FB1_12  29   I/O     I     
(unused)                      0     FB1_13  28   I/O     I     
(unused)                      0     FB1_14  27   I/O     I     
(unused)                      0     FB1_15  26   I/O     I     
sig_mapcond                   6     FB1_16  25   I/O     I                 

Signals Used by Logic in Function Block
  1: A<0>               7: A<2>              13: A<8> 
  2: A<10>              8: A<3>              14: A<9> 
  3: A<11>              9: A<4>              15: M1 
  4: A<12>             10: A<5>              16: romacc 
  5: A<13>             11: A<6>              17: sig_mapcond 
  6: A<1>              12: A<7>             

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
mapterm           XXXXXXXXXXXXXXXX........................ 16      
ideio0            X....XXXXX.X............................ 7       
ideio1            X....X...XXX............................ 5       
automap           ................X....................... 1       
mapcond           ................X....................... 1       
sig_mapcond       XXXXXXXXXXXXXXXXX....................... 17      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB2  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB2_1   1    I/O     I     
(unused)                      0     FB2_2   2    I/O     I     
(unused)                      0     FB2_3   3    I/O     I     
(unused)                      0     FB2_4   4    I/O     I     
(unused)                      0     FB2_5   5    GCK/I/O GCK   
(unused)                      0     FB2_6   6    GCK/I/O I     
(unused)                      0     FB2_7   7    GCK/I/O       
(unused)                      0     FB2_8   8    I/O           
(unused)                      0     FB2_9   9    I/O           
(unused)                      0     FB2_10  11   I/O           
(unused)                      0     FB2_11  12   I/O           
(unused)                      0     FB2_12  14   I/O           
(unused)                      0     FB2_13  18   I/O           
(unused)                      0     FB2_14  19   I/O           
(unused)                      0     FB2_15  20   I/O           
(unused)                      0     FB2_16  22   I/O           
*******************************  Equations  ********************************

********** Mapped Logic **********

FDCPE_automap: FDCPE port map (automap,sig_mapcond,CLOCK,'0','0','1');


ideio0 <= (A(7) AND A(5) AND NOT A(4) AND NOT A(3) AND A(1) AND A(0) AND 
	NOT A(2));


ideio1 <= (A(7) AND A(5) AND NOT A(6) AND A(1) AND A(0));

FDCPE_mapcond: FDCPE port map (mapcond,sig_mapcond,CLOCK,'0','0','1');


mapterm <= ((NOT A(7) AND NOT A(5) AND NOT A(4) AND NOT A(13) AND NOT A(12) AND NOT A(11) AND 
	NOT A(10) AND romacc AND M1 AND NOT A(9) AND NOT A(8) AND NOT A(6) AND NOT A(1) AND 
	NOT A(0) AND NOT A(2))
	OR (A(7) AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT A(13) AND NOT A(12) AND 
	NOT A(11) AND A(10) AND romacc AND M1 AND NOT A(9) AND NOT A(8) AND A(6) AND 
	A(1) AND NOT A(0) AND A(2))
	OR (NOT A(7) AND A(5) AND A(4) AND A(3) AND NOT A(13) AND NOT A(12) AND 
	NOT A(11) AND NOT A(10) AND romacc AND M1 AND NOT A(9) AND NOT A(8) AND NOT A(6) AND 
	NOT A(1) AND NOT A(0) AND NOT A(2))
	OR (NOT A(7) AND A(5) AND NOT A(4) AND NOT A(3) AND NOT A(13) AND NOT A(12) AND 
	NOT A(11) AND A(10) AND romacc AND M1 AND NOT A(9) AND A(8) AND A(6) AND 
	A(1) AND NOT A(0) AND NOT A(2))
	OR (NOT A(7) AND A(5) AND NOT A(4) AND NOT A(3) AND NOT A(13) AND NOT A(12) AND 
	NOT A(11) AND NOT A(10) AND romacc AND M1 AND NOT A(9) AND NOT A(8) AND A(6) AND 
	A(1) AND NOT A(0) AND A(2)));

FTCPE_sig_mapcond: FTCPE port map (sig_mapcond,sig_mapcond_T,CLOCK,'0','0','1');
sig_mapcond_T <= ((sig_mapcond AND A(7) AND A(5) AND A(4) AND A(3) AND 
	NOT A(13) AND A(12) AND A(11) AND A(10) AND romacc AND M1 AND A(9) AND 
	A(8) AND A(6))
	OR (NOT sig_mapcond AND NOT A(7) AND NOT A(5) AND NOT A(4) AND NOT A(13) AND 
	NOT A(12) AND NOT A(11) AND NOT A(10) AND romacc AND M1 AND NOT A(9) AND NOT A(8) AND 
	NOT A(6) AND NOT A(1) AND NOT A(0) AND NOT A(2))
	OR (NOT sig_mapcond AND A(7) AND NOT A(5) AND NOT A(4) AND NOT A(3) AND 
	NOT A(13) AND NOT A(12) AND NOT A(11) AND A(10) AND romacc AND M1 AND NOT A(9) AND 
	NOT A(8) AND A(6) AND A(1) AND NOT A(0) AND A(2))
	OR (NOT sig_mapcond AND NOT A(7) AND A(5) AND A(4) AND A(3) AND 
	NOT A(13) AND NOT A(12) AND NOT A(11) AND NOT A(10) AND romacc AND M1 AND NOT A(9) AND 
	NOT A(8) AND NOT A(6) AND NOT A(1) AND NOT A(0) AND NOT A(2))
	OR (NOT sig_mapcond AND NOT A(7) AND A(5) AND NOT A(4) AND NOT A(3) AND 
	NOT A(13) AND NOT A(12) AND NOT A(11) AND A(10) AND romacc AND M1 AND NOT A(9) AND 
	A(8) AND A(6) AND A(1) AND NOT A(0) AND NOT A(2))
	OR (NOT sig_mapcond AND NOT A(7) AND A(5) AND NOT A(4) AND NOT A(3) AND 
	NOT A(13) AND NOT A(12) AND NOT A(11) AND NOT A(10) AND romacc AND M1 AND NOT A(9) AND 
	NOT A(8) AND A(6) AND A(1) AND NOT A(0) AND A(2)));


Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FDDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 FTDCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC2C32A-4-PC44


   --------------------------------  
  /6  5  4  3  2  1  44 43 42 41 40 \
 | 7                             39 | 
 | 8                             38 | 
 | 9                             37 | 
 | 10                            36 | 
 | 11        XC2C32A-4-PC44      35 | 
 | 12                            34 | 
 | 13                            33 | 
 | 14                            32 | 
 | 15                            31 | 
 | 16                            30 | 
 | 17                            29 | 
 \ 18 19 20 21 22 23 24 25 26 27 28 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 A<7>                             23 GND                           
  2 A<8>                             24 KPR                           
  3 A<9>                             25 A<6>                          
  4 M1                               26 A<5>                          
  5 CLOCK                            27 A<4>                          
  6 romacc                           28 A<3>                          
  7 KPR                              29 A<2>                          
  8 KPR                              30 TDO                           
  9 KPR                              31 GND                           
 10 GND                              32 VCCIO-1.8                     
 11 KPR                              33 A<1>                          
 12 KPR                              34 A<13>                         
 13 VCCIO-1.8                        35 A<12>                         
 14 KPR                              36 A<11>                         
 15 TDI                              37 A<10>                         
 16 TMS                              38 A<0>                          
 17 TCK                              39 mapcond                       
 18 KPR                              40 automap                       
 19 KPR                              41 VCCAUX                        
 20 KPR                              42 ideio1                        
 21 VCC                              43 ideio0                        
 22 KPR                              44 mapterm                       


Legend :  NC  = Not Connected, unbonded pin
        PGND  = Unused I/O configured as additional Ground pin
         KPR  = Unused I/O with weak keeper (leave unconnected)
         WPU  = Unused I/O with weak pull up (leave unconnected)
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
      VCCAUX  = Power supply for JTAG pins
   VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
   VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
   VCCIO-1.8  = I/O supply voltage for LVCMOS18
   VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
        VREF  = Reference voltage for indicated input standard
       *VREF  = Reference voltage pin selected by software
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc2c*-*-*
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Set Unused I/O Pin Termination              : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Enable Input Registers                      : ON
Function Block Fan-in Limit                 : 38
Use DATA_GATE Attribute                     : ON
Set Tristate Outputs to Termination Mode    : KEEPER
Default Voltage Standard for All Outputs    : LVCMOS18
Input Limit                                 : 32
Pterm Limit                                 : 28
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